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Second IEEE International Workshop on
Testing Three-Dimensional Stacked Integrated Circuits
(3D-Test 2011)
September 22-23, 2011
Disneyland Hotel
Anaheim, California, USA

http://3dtest.tttc-events.org

in conjunction with ITC/Test Week 2011

ADVANCE REGISTRATION DEADLINE SEPTEMBER 2, 2011!
CALL FOR PARTICIPATION

Scope -- Key Dates -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope
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The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.

You are invited to participate in the workshop. Participation requires registration and a registration fee. Workshop registration includes all technical sessions, Electronic Workshop Digest (containing extended abstracts, papers, slides, posters, as far as made available by their presenters), workshop reception, continental breakfast, lunch, and break refreshments. On-line registration is available via the workshop’s website (http://3dtest.tttc-events.org). Advance (discount) registration is available till September 2, 2011. Alternatively, register on-site during Test Week at the ITC Registration Counter at the Disneyland Hotel; admission for on-site registrants is subject to availability.

Poster submission is still open till September 2, 2011.
Key Dates
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Advance Discount Registration Deadline: September 2, 2011
Poster Submission Deadline: September 2, 2011
Workshop Registration
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On-line registration is available via the workshop’s website (http://3dtest.tttc-events.org).
Advance Program
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Thursday -- Friday

September 22, 2011 (Thursday)
 
4:00 PM - 5:30 PM Session 1: Opening
Moderator: Peter Maxwell – Aptina Imaging, USA
4:00 - 4:15

Welcome Message
General Chair: Yervant Zorian – Synopsys, USA
Program Chair: Erik Jan Marinissen – IMEC, B
4:15 - 5:00

Keynote Address : 3-D SoC Packaging for Smart Mobile Devices: Current State and Challenges
Hong Hao – Samsung Semiconductor, USA

5:00 - 5:30

Invited Address: 3D TSV Infrastructure: Challenges and Opportunities
E. Jan Vardaman – TechSearch International, USA
 
5:30 PM - 6:30 PM Session 2 - Panel Discussion: Executive Views on 3D-Test Challenges and Solutions
Moderator: Yervant Zorian – Synopsys, USA
Co-organized with Herb Reiter, GSA / 3D-IC Working Group
 

Panelists:

Calvin Cheung – ASE, USA
Hong Hao – Samsung Semiconductor, USA
Brad Robbins – Teradyne, USA
Sanjiv Taneja – Cadence Design Systems, USA
 
6:30 PM - 7:00 PM Session 3 - Posters and Demos
 

Poster 1: Test Cost Modeling for 3D-Stacked ICs
Mottaqiallah Taouil, Said Hamdioui – TU Delft, NL; Erik Jan Marinissen – IMEC, BE
  Poster 2: 3D SIC’s Reliability Investigation by Examination of Mechanical Stress Sensitive MOS Transistors and CNT’s in Dedicated Test Structures
T. Bieniek, G. Janczyk, P. GHrabiec, J. Szynka – Institute of Electron Technology, PL
  Poster 3: What Could be Hiding in Your 3D Silicon? Trojans and Counterfeits May Be Lurking in the 3D Stack
Jennifer Dworak – Southern Methodist University, USA; Al Crouch – Asset Intertech, USA
  Poster 4: Wideband Ultralow Impedance Evaluation System of Power Distribution Network for Decoupling Capacitor Embedded Interposers of 3-D Integrated LSI System
Katsuya Kikuchi, Masahiro Aoyagi – AIST, JP; Toshio Gomyo, Toshikazu Ookubo – ASET, JP; Toshio Sudo – Shibaura Institute of Technology, JP; Kanji Otsuka – Meisei University, JP
  Table Top Demos
 

Demo 1: DFT Insertion and Interconnect TG for 3D Stacked ICs
Brion Keller – Cadence Design Systems, USA
  Demo 2: IEEE 1149.1-2011, multi-TAP iMajik and Concurrent JTAG for 3D-SICs
Brian Turmelle, Craig Stephen – Intellitech, USA
  Demo 3: Moving IC Test in a New Direction
Steve Pateras – Mentor Graphics, USA
  Demo 4: New Publications from Springer of Interest to Attendees of 3D-TEST Workshop
Charles Glaser – Springer, USA
  Demo 5: Synthesis-Based Test for 3D-IC
Adam Cron – Synopsys, USA
  Demo 6: Cost Trade Off Analysis Tools
E. Jan Vardaman – TechSearch International, USA
 
7:00 PM - 9:00 PM WORKSHOP RECEPTION
 
September 23, 2011 (Friday)
 
7:00 AM - 8:00 AM WORKSHOP BREAKFAST
 
8:00 AM - 9:00 AM Session 4 - Research
Moderator: Sudipta Bhawmik – Qualcomm, USA
8:00 - 8:15

Thermal-Aware Test Scheduling for 3D ICs
Chih-Yao Hsu, Chun-Yi Kao, James C.-M. Li – National Taiwan University, TW; Krishnendu Chakrabarty – Duke University, USA
8:15 - 8:30
Variable Output Thresholding: A Robust Delay Measurement Scheme for TSV
Shi-Yu Huang, Yu-Hsiang – National Tsing Hua University, TW; Ding-Ming Kwai – ITRI, TW
8:30 - 8:45
Test Planning for 3D Stacked ICs with Through-Silicon Vias
Breeta SenGupta, Urban Ingelsson, Erik Larsson – Linköping University, SE
8:45 - 9:00

Pre-Bond Testing of Die Logic and TSVs in High Performance 3D-SICs
Brandon Noia, Krishnendu Chakrabarty – Duke University, USA           

 
9:00 AM - 10:00 AM Session 5 - Electronic Design Automation
Moderator: Saman Adham – TSMC, USA
9:00 - 9:15

Automation of 3D DfT Insertion
Sergej Deutsch – Cadence, DE; Vivek Chickermane, Brion Keller – Cadence, USA; Subhasish Mukherjee – Cadence, IN; Mario Konijnenburg – IMEC/Holst Centre, NL; Erik Jan Marinissen – IMEC, BE; Sandeep K. Goel – TSMC, USA
9:15 - 9:30
DFT and Test Flows for Stacked Die
Steve Pateras, David Buck – Mentor Graphics, USA
9:30 - 9:45
3D Design, Test Technology, and Standardization
Adam Cron – Synopsys, USA
9:45 - 10:00
Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing
Laung-Terng Wang, Shianling Wu, Manish Bhattarai, Fangfang Li, Zhigang Jiang – SynTest Technologies, USA; Nur A. Touba – University of Texas, USA; Michael S. Hsiao – Virginia Tech, USA; Jiun-Lang Huang, James Chien-Mo Li – National Taiwan University, TW; Xiaoqing Wen – Kyushu Institute of Technology, JP
 
10:00 AM - 10:45 AM Session 6 - Posters and Demos
See listing above. (Coffee and Tea)
 
10:45 AM - 11:30 AM Session 7 - Wafer Probing
Moderator: Amy Leong – MicroProbe, USA
10:45 - 11:00

Probing Stategies for Through-Silicon Stacking
Eric Strid, Ken Smith, Peter Hanaway, Reed Gleason – Cascade Microtech, USA
11:00 - 11:15
Challenges and Solutions for Testing of TSV and Micro-Bump
Ben Eldridge, Marc Loranger – FormFactor, USA
11:15 - 11:30

A Low-Force MEMS Probe Solution for Fine-Pitch 3D-SIC Wafer Test
Matt Losey, Robert Smith, Florent Cros, Yohannes Desta, Lakshmi Namburi, Melvin Khoo – Touchdown Technologies, USA
 
11:30 AM - 12:00 PM Session 8 - Standardization
Moderator: Dan Hamling – GE Capital, USA
11:30 - 1:45

Standards for 3D Stacked Integrated Circuits
Richard A. Allen – NIST, USA; Larry Smith – Sematech, USA
11:45 - 12:00
Status Update of IEEE P1838
Erik Jan Marinissen – IMEC, BE; Adam Cron – Synopsys, USA
 
12:00 NOON - 1:00 PM WORKSHOP LUNCHEON
 
1:00 PM - 1:30 PM Session 9 - Posters and Demos
See listing above.
 
1:30 PM - 2:30 PM Session 10 - Applications
Moderator: Dan Rishavy – TEL Test Systems, USA
1:30 - 1:45

Product Level Screening of Latent Defects in Through Silicon Vias
Cathal Cassidy, Simon Watts – Austria Microsystems, A
1:45 - 2:00
Test Challenges in 3D TSV SOC
Amer Cassier – Qualcomm, USA
2:00 - 2:15
Electro-Migration Behavior of 3D-IC TSV – Comparison of Usual Thin Metal Line vs. Thick Metal Line Process
Thomas Frank, C. Chappaz, L. Arnaud, F. Lorut – STMicroelectronics, FR; S. Moreau, P. Leduc, A. Thuaire – CEA-LETI, FR; Lorena Anghel – TIMA, FR
2:15 - 2:30
Realize Dynamic Testing Based on Thermal Perspective
Chen Hao, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng – TSMC, TW
 
2:30 PM - 4:00 PM Session 11 - PANEL DISCUSSION: Test Challenges and Solutions for (Wide-I/O) DRAM Stacking
Moderator: Bill Eklow – Cisco Systems, USA
 

Panelists:

Gary Fleeman – Advantest, USA
Sandeep K. Goel – TSMC, USA
Marc Greenberg – Cadence Design Systems, USA
Michael Laisne – Qualcomm, USA
Mike Ricchetti - AMD, USA
 
4:00 PM WORKSHOP CLOSURE
 
More Information
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Yervant Zorian – General Chair
Synopsys
700 East Middlefield Road
Mountain View, CA 94043-4033, USA
Tel.: +1 (650) 584-7120

Erik Jan Marinissen – Program Chair
IMEC vzw
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +32 (0)16 28-8755
Committees
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General Chair:
Y. Zorian – Synopsys (US)

Program Chair:
E.J. Marinissen – IMEC (B)

Finance Chair:
Said Hamdioui – TU Delft (NL)

Publication Chair:
M. Grosso – Politecnico di Torino (I)

Publicity Chair:
F. von Trapp – 3DInCites (US)

Web Chair:
G. Jervan – Tallinn Univ. of Techn. (EE)

Local Arrangements Chair:
J. Potter – Asset Intertech (US)

Program Committee Members:
S. Adham  – TSMC (CAN)
V. Agrawal – Auburn Univ. (US)
M. Banke – Altera (US)
S. Bhatia – Oasys (US)
C. Bullock – Texas Instruments (US)
K. Chakrabarty – Duke Univ. (US)
S. Chakravarty – LSI (US)
V. Chickermane – Cadence (US)
E. Cormack – DfT Solutions (UK)
A. Crouch – Asset Intertech (US)
T. Eaton – Cisco Systems (US)
P. Emmett – Powertech (US)
S.K. Goel – TSMC (US)
G. Fleeman – Advantest (US)
M.-L. Flottes – LIRMM (F)
P. Franzon – NC State Univ. (US)
M. Higgins – Analog Devices (IRL)
C.-L. Hsu – ITRI (TW)
S.-Y. Huang – NTHU (TW)
R. Kapur – Synopsys (US)
M. Knox – IBM (US)
M. Laisne – Qualcomm (US)
P. Lebourg – ST Microelectronics (F)
S. Lecomte – ST-Ericsson (F)
H.-H. Lee – Georgia Tech (US)
I. Loi – Universita di Bologna (I)
M. Loranger – FormFactor (US)
C. Mayor – Presto Engineering (F)
T. McLaurin – ARM (US)
K. Parker – Agilent Technologies (US)
S. Pateras – Mentor Graphics (US)
B. Patti – Tezzaron Semiconductor (US)
F. Pöhl – Intel (D)
M. Ricchetti – AMD (US)
D. Rishavy – TEL Test Systems (US)
T. Thärigen – Cascade Microtech (D)
E. Volkerink – Verigy (US)
Y. Xie – Penn. State Univ. (US)
Q. Xu – Chinese Univ. Hong Kong (HK)
M. Zhang – Samsung Electronics (US)
For more information, visit us on the web at: http://3dtest.tttc-events.org

The Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test 2011) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Joan FIGUERAS
UPC Barcelona Tech - Spain
Tel. +
E-mail figueras@eel.upc.edu

ITC GENERAL CHAIR
Doug YOUNG
- USA
Tel. +1-602-617-0393
E-mail doug0037@aol.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS
University of Athens - Greece
Tel. +30-210-7275145
E-mail dgizop@di.uoa.gr

STANDARDS
Rohit KAPUR
Synopsys, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

  

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG
Alcatel-Lucent - USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
Krish CHAKRABARTY
Duke University - USA
Tel. +1-
E-mail krish@ee.duke.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent - USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL ACTIVITIES
Patrick GIRARD
LIRMM – France
Tel.+33 467 418 629
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel. +81 743 72 5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com